Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis

<p><span>The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with features added advantage performing complex algorithms high-performance computations. This manuscript implements an efficient arithmetic (RFPA) unit, and its performance metrics realized detail. RFP adder/subtractor (A/S), multiplier, divider units designed as a part of unit. RFPA unit is by considering basic gates. mantissa multiplier created using 24x24 Wallace tree multiplier. In contrast, reciprocal Newton Raphson’s method. submodules executed parallel utilizing one clock cycle individually. synthesized separately on Vivado IDE environment obtained implementation results Artix-7 field programmable gate array (FPGA). utilizes only 18.44% slice look-up tables (LUTs) consuming 0.891 W total FPGA. sub-models compared existing approaches better chip resource utilization improvements.</span></p>